1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a semiconductor memory device having a function of trimming the variation in threshold voltages of memory cells. Moreover, the present invention relates to a trimming method of the threshold voltage using such a semiconductor memory device.
2. Description of the Related Art
In recent years, for improving the integration of the semiconductor memory device, a size of a transistor forming a memory cell or a sense amplifier is downsized. Moreover, a threshold voltage of the transistor is also made lower with the reduction of the power supply voltage. Thus, variation (offset) of threshold voltages of the transistors included in memory cells or sense amplifiers greatly affect operation of the memory cells or the sense amplifiers.
Particularly, in SRAM, offset of transistors included in memory cells reduces a static noise margin (referred to as SNM hereinbelow) of the memory cell. A memory cell with a low SNM is unstable in operation. Thus, when a minute voltage caused by noise or the like is applied from a bit line, false writing (disturb) occurs at a memory cell due to such the minute voltage. Moreover, the transistor included in the sense amplifier may have offset. In this case, the operation of the sense amplifier is delayed until the signal level on the bit line increase to be larger than the offset.
A method for solving an above-mentioned problem is disclosed in JP 10-162585A. In this method, a semiconductor memory device includes therein a structure for trimming offset. In addition, a voltage suitable for amount of trimming is applied to a transistor included in the memory cell or the sense amplifier.
However, in the method, it is necessary to provide trimming means and trimming amount adjustment means in addition to a memory cell and a sense amplifier. Thus, the area of the semiconductor memory device may increase.
Moreover, since this method needs trimming of the memory cells or sense amplifiers on a one-by-one basis, it needs a lot of time to trim all memory cells or sense amplifiers in the semiconductor memory device.
Therefore, in the conventional art, it is difficult to provide a semiconductor memory device that can trim offset of the memory cell with a high efficiency while avoiding the area of the semiconductor memory device from being large.